Design and Testing Parallel Prefix Adders using Reconfigurable LFSR in FPGA
نویسندگان
چکیده
منابع مشابه
Design and Characterization of Fault Tolerant Power Parallel Prefix Adders using FPGA Design
Parallel-prefix adders (also known as carry tree adders) are known to have the best performance in VLSI designs. However, this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and...
متن کاملDesign of High Speed 128 bit Parallel Prefix Adders
In this paper, we propose 128-bit Kogge-Stone, Ladner-Fischer, Spanning tree parallel prefix adders and compared with Ripple carry adder. In general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix adders because of their advantages comp...
متن کاملDesign of High-Speed Low-Power Parallel-Prefix VLSI Adders
Parallel-prefix adders offer a highly-efficient solution to the binary addition problem. Several parallel-prefix adder topologies have been presented that exhibit various area and delay characteristics. However, no methodology has been reported so far that directly aims to the reduction of switching activity of the carry-computation unit. In this paper by reformulating the carry equations, we i...
متن کاملSpeed Comparison Parallel Prefix Adders with RCA and CSA in FPGA
The Adders are the critical elements in most of the digital circuit designs, including digital signal processors (DSP) and microprocessors. Extensive research has gone into the VLSI implementations of Parallel Prefix Adders which are known for their best performance. The performance of Parallel Prefix Adders is directly affected by the constraints in the logic implementations of Parallel Prefix...
متن کاملDesign and Implementation of RNS Reverse Converter using Parallel Prefix Adders
The implementation of residue number system reverse converters based on well-known regular and modular parallel prefix adders is analyzed. The VLSI implementation results show a significant delay reduction and area × time2 improvements, all this at the cost of higher power consumption, which is the main reason preventing the use of parallel-prefix adders to achieve high-speed reverse converters...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal for Research in Applied Science and Engineering Technology
سال: 2019
ISSN: 2321-9653
DOI: 10.22214/ijraset.2019.4630